The present invention relates to semiconductor memory devices and, more particularly, to a technology for improving latency of a RAS (row address strobe) signal of a semiconductor memory device, such as DRAM, appropriate to a low voltage operation implemented by a BSG (boosted sense ground) circuit technology.
An example of the prior art, a semiconductor memory device is described in a Japanese patent application of laid-open No. Bei 11-87,649, which was published on Mar. 30, 1999 and is assigned to Tokkai. The semiconductor memory device of that application includes a memory cell array having a plurality of memory cells arrayed in a grid-shape at crossing points of a multiplicity of word lines and a plurality of bit lines and sense amplifiers for amplifying data stored in the memory cells, a decoder for selecting an arbitrary cell from the memory cell array and an input/output (I/O) control circuit for performing I/O control related to data reading and writing for the memory cell selected by the decoder. In order to sufficiently secure an amount of signals of the bit lines, the sense amplifier employs a BSG circuit and the memory cells are formed on an SOI (silicon-oxide-insulator) substrate. However, this circuit configuration has severe problems in that, as a supply voltage is reduced, the driving voltage of the sense amplifiers decreases in an active mode, so that an operational speed may be delayed or the sensing operation may fail.
Another exemplary circuit configuration of the prior art will be explained herein below.
Referring to FIGS. 5A and 5B, there are illustrated a configuration of a sense amplifier driving unit in accordance with an example of the prior art and a voltage waveform of the sense amplifier driving unit and a corresponding sense amplifier.
When the sense amplifier driving unit is employed, a voltage Vcell0 is coupled to a pull-up source line CSP of the sense amplifier in response to a PSA driving signal SPSA and a ground voltage Vss is provided to a pull-down source line CSN of the sense amplifier in response to a Vss driving signal SVss. That is, in an active mode, a voltage, Vgs, shown in equation EQ. 1 below, is coupled between a gate and a source of an NMOS sense amplifier.                     Vgs        =                              Vcell            ⁢                          xe2x80x83                        ⁢            0                    2                                    EQ        .                  xe2x80x83                ⁢        1            
Referring to FIGS. 6A and 6B, there are depicted a configuration of a sense amplifier driving unit in accordance with another example of the prior art, which employs a BSG technology, and a voltage waveform of the sense amplifier driving unit and a corresponding sense amplifier.
According to the BSG technology, the pull-down source line CSN of the sense amplifier is driven by a voltage Vbsg higher than the ground voltage Vss.
Likewise, when employing the sense amplifier driving unit, a voltage Vcell1 (=Vcell0+Vbsg) is provided to the pull-up source line CSP of the sense amplifier in response to the PSA driving signal SPSA and the boosted ground voltage Vbsg is supplied to the pull-down source line CSN of the sense amplifier in response to a boosted ground voltage Vbsg driving signal SVbsg. Therefore, in an active mode, a voltage, Vgs, described in equation EQ. 2 below, is provided between a gate and a source of an NMOS sense amplifier.                     Vgs        =                                                            Vcell                ⁢                                  xe2x80x83                                ⁢                1                            -              Vbsg                        2                    =                                    Vcell              ⁢                              xe2x80x83                            ⁢              0                        2                                              EQ        .                  xe2x80x83                ⁢        2            
That is, regardless of employing the BSG circuit, in the active mode, the voltage Vgs coupled between the gate and the source of the NMOS sense amplifier has a constant value Vcell0/2 and, therefore, it is difficult to improve an operational speed under a low supply voltage since it is impossible to sufficiently raise the driving voltage of the sense amplifier.
Further, since the conventional BSG technology uses the voltage Vbsg separately generated inside a chip, a problem in stability of the sensing operation may occur due to increased noise in the early sensing operation consuming a lot of current.
It is, therefore, a primary object of the present invention to provide a semiconductor memory device employing a BSG circuit for improving its sensing speed by additionally securing a driving voltage of a sense amplifier in a low supply voltage operation.
Another object of the present invention is to provide a semiconductor memory device for enhancing stability of its sensing operation by reducing noise generated in the early sensing operation of a sense amplifier.
Still another object of the present invention is to provide a sense amplifier driving method for use in a semiconductor memory device for improving an operational speed and operational stability when a low supply voltage is supplied.
In accordance with an aspect of the present invention, there is provided a semiconductor memory device comprising a sense amplifier for amplifying memory cell data; a sense amplifier driving unit for driving a pull-up source line and a pull-down source line of the sense amplifier and sequentially driving the pull-down source line CSN into a ground voltage and a boosted ground voltage in response to a first control signal and a second control signal; a sense amplifier driving control unit for generating the first control signal and the second control signal and setting a ground voltage driving time of the pull-down source line by adjusting timing of the first control signal; and a boosted ground voltage generating unit for producing the boosted ground voltage.
In accordance with another aspect of the present invention, there is provided a semiconductor memory device comprising a sense amplifier for amplifying memory cell data; a sense amplifier driving means having a first sense amplifier driving line connected to a cell voltage providing sector and a second sense amplifier driving line attached to a ground voltage providing sector and a boosted ground voltage providing sector in parallel; a sense amplifier driving control means for controlling the cell voltage providing sector, the ground voltage providing sector and the boosted ground voltage providing sector; and a boosted ground voltage generating means for producing a boosted ground voltage to thereby provide the boosted ground voltage to the sense amplifier driving means.
In accordance with still another aspect of the present invention, there is provided a method for driving a sense amplifier including a pull-up source line and a pull-down source line, which comprises steps of (a) initially driving the pull-up source line to a ground voltage; and (b) driving the pull-up source line to a boosted ground voltage after performing the step (a), wherein the pull-up source line is driven by a cell voltage.